Many electronically monitored and controlled systems, such as may be found in an automobile, are comprised of systems having a distributed architecture. More particularly, such systems comprise a collection of modules, and these modules typically run somewhat independently of one another, though a certain amount of intercommunication between the modules must be maintained. Rather than having a dedicated communications line between every two modules in a particular system, a single multiple access communications link will typically be substituted.
By using a single, serial, bi-directional, multiple access communication link, the required number of conductors can be minimized along with overall cost. By the same token, however, certain safeguards must be provided to minimize error or a mission disabling failure.
A typical prior art differential voltage transmission system as used with twisted pair transmission lines has been set forth in FIG. 1. This system includes a first resistor (R1) connected between a positive 5 volt source and the collector of an emitter grounded transistor (Q1). A second resistor (R2) connects between ground and the collector of another transistor (Q2) having its emitter connected to the positive 5 volt source. The bases of both transistors (Q1 and Q2) connect to appropriate triggering circuitry as well known in the art.
A comparator comprises the prior art receiver mechanism as indicated, and essentially subtracts the V.sub.2 voltage as appears at the collector of the second transistor (Q2) from the V.sub.1 voltage as appears at the collector of the first transistor (Q1). If CMOS devices are used and a supply voltage of +5 volts provided, then analog signals in excess of 2.5 volts will be accepted as logical 1's and signals below this threshold will be interpreted as logic 0's.
With reference to FIG. 2, it can be seen that when both transistors (Q1 and Q2) are turned off, V.sub.1 will exceed the 2.5 volts threshold, and V.sub.2 will fall short of the threshold. As a result, the difference between the two will be as indicated on the graph. As can be seen, a relative logic high can be easily distinguished from a relative logic low by the comparator when no fault conditions have occurred. In this way, then, serially transmitted digitally encoded data can be transmitted through the transmission system between various modules.
This prior art configuration provides very good common mode rejection of interference. Unfortunately, this structure does not tolerate certain fault conditions in the transmission system. Such fault conditions can be specifically defined and categorized as follows:
(1) The first transistor is constantly turned on; PA1 (2) The second transistor is constantly turned on; PA1 (3) The first transistor never turns on; PA1 (4) The second transistor never turns on; PA1 (5) The transmission line associated with the first transistor opens; PA1 (6) The transmission line associated with the second transistor opens; PA1 (7) The first transmission line shorts to the positive voltage source; PA1 (8) The first transmission line shorts to ground; PA1 (9) The second transmission line shorts to the positive voltage source; or PA1 (10) The second transmission line shorts to ground.
Should any one of the above fault conditions occur, the prior art receiver will not be able to properly decode the incoming signals. To accomodate this problem to some extent, the prior art does suggest that redundant links, redundant drivers and even redundant receivers can be utilized. The provision of such redundant parts increases the cost of the system and, in the long run, may only postpone an inevitable and unexpected complete failure of the system.
A need therefore exists for a fault tolerant receiver that can receive and properly decode differential voltage level signals even though the transmission system may have suffered a fault condition.